The present invention relates to a variable clock delay circuit utilizing the resistance-capacitance time constant (resistance capacitance: R.C.).
Generally, semiconductor memory devices require times different delay times between various operating clock signals according to their use. Therefore, in order to perform such functions, various clock generators are packaged in semiconductor memory devices according to their use. However, clock generators generate the clocks with predetermined timing according to the use thereof, on the basis of the periods of generators providing the clock signals. Thus, in order to make the desired predetermined timing variable, a delay circuit is used.
FIG. 1 shows a conventional clock delay circuit in which a first clock generator 100 is connected through a variable resistor 111 to a node 113, said node 113 is connected with a capacitor 112 to be grounded, and to an output terminal connecting said resistor 111 in parallel with said capacitor 112 is connected a second clock generator 200, thereby generating the desired clock signal.
FIG. 2A is a circuit showing in detail the required one part of the first and second clock generators 100 and 200, and FIG. 2B is a timing chart for explaining the operation of the circuit shown in FIG. 2A in which 2a shows an input signal waveform occurring at a precharge clock terminal 202, 2b shows one example of input waveform occurring at the signal input terminal 201, and 2c shows one example of an output waveform occurring at the signal output terminal 203.
The operation of the conventional clock delay circuit described above will be explained with reference to FIGS. 1 and 2.
In FIG. 1, when the output of the first clock generator 100, i.e., the node 101, goes to the "high" level, the capacitor 112 is charged up through the variable resistor 111 and the signal of the "high" level is applied through the node 113 to the input terminal of the second clock generator 200 so that said second clock generator 200 may be driven, thereby generating a variable clock regulated in dependence upon the predetermined delay by the drive of said second clock generator 200.
Now, the conventional operation of the example of FIG. 2A will be described in detail.
When a nMOS transistor 3 is turned ON by the "high" level 221 of the precharge clock signal of waveform 2a shown in FIG. 2B, the voltage at a node 15 becomes O[V]. Therefore, the voltage applied to a node 14 by the nMOS transistor 4 is charged by the power source voltage Vcc minus the threshold voltage Vt of the nMOS transistor 2, (Vcc-Vt). At this time, when the input voltage signal 2b at the input voltage terminal 201 goes to the "high" level 222, the voltage applied to the node 15 becomes the input voltage Vin minus the threshold voltage Vt of the nMOS transistor 3, (Vin-Vt). Then if the value of Vin-Vt is greater than the value of Vt (Vin-Vt&gt;Vt), the nMOS transistor 2 is turned ON. Therefore, node 14 is discharged to O[V], and the nMOS transistors 10 and 12 are turned OFF. Accordingly, a "high" signal 223 of waveform 2c shown in FIG. 2B occurs at the output terminal 203. That is to say, if the input voltage Vin at terminal 201 exceeds 2Vt (Vin&gt;Vt+Vt), then at the output terminal 203 the signal shown as waveform 2c occurs.
When said output is varied by the power source voltage at the node 101 in FIG. 1, the voltage at the node 113 varies by 63% of the power source voltage Vcc after the predetermined time constant [.tau.=R(111) C(112)] depending on the values of the variable resistor (111) and the capacitor (112). Due to this, there has been produced a problem of impractical use in which, when the input voltage Vin exceeds 2 Vt, the signal occurring at the output terminal 203 does not obtain the desired effect of the predetermined RC time constant. That is, when the power source voltage is 5V and the threshold voltage Vt is 0.8V, the input voltage of the second clock generator 200 after one RC time constant is 3.16V (5V.multidot.0.63).
However, since, before that, i.e. when Vin=2Vt=1.6V, the output at the output terminal 203 is produced from the second clock generator 200, the effect of the time constant is accomplished only to the half extent. If the power source voltage Vcc is 3V, the input voltage Vin after one RC time constant is 1.98V (3V.times.0.63) at the node 101. Accordingly, since, when Vin=2Vt=1.6V, a clock is produced from the second clock generator 200, the regulated delay between the clocks is obtained to the extent approximately equal to the time constant.
As described above, in the conventional clock delay circuit, the variation in width of the delay between the clocks according to the variation of the power source voltage Vcc is large. That is, a small amount of delay is obtained at the "high" of power source voltage Vcc and a large amount of delay is obtained at the "low" of power source voltage Vcc. Therefore, the stabilization of operation is not accomplished.